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jbdavid
  • Member for 10 years, 11 months
  • Last seen more than 10 years ago
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Mixed Signal Design Verification languages: -Verilog (in all its flavors esp Verilog-AMS) -perl -SKILL (the cadence variant of LISP) -(someday) Python & Matlab
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How to ADD one module to initrd using mkinitrd
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Testing ladder logic
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How to ADD one module to initrd using mkinitrd

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