101
reputation
1
jbdavid
Mixed Signal Design Verification
languages:
-Verilog (in all its flavors esp Verilog-AMS)
-perl
-SKILL (the cadence variant of LISP)
-(someday) Python & Matlab
-
San Jose, CA
-
Member for 9 years, 7 months
-
2 profile views
-
Last seen Aug 2 '11 at 0:33
Communities (6)
Top network posts
Keeping a low profile.
This user hasn't posted yet.
