101
reputation
1
jbdavid
Mixed Signal Design Verification
languages:
-Verilog (in all its flavors esp Verilog-AMS)
-perl
-SKILL (the cadence variant of LISP)
-(someday) Python & Matlab
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San Jose, CA
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Member for 9 years, 5 months
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2 profile views
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Last seen Aug 2 '11 at 0:33
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