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1

There were two issues preventing the compiling of the program. First, as answered by steeldriver, the library path was not correctly included and the libs were not correctly referenced in GCC. Second, several cpp source files were missing, either accidentally deleted or not successfully decompressed from the archive the first time. Once these issues were ...


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Included in linux-image the name is atlantic (output from debian buster): $ modinfo atlantic filename: /lib/modules/4.19.0-13-amd64/kernel/drivers/net/ethernet/aquantia/atlantic/atlantic.ko description: aQuantia Corporation(R) Network Driver author: aQuantia version: 2.0.3.0-kern license: GPL v2 To load the driver: sudo ...


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You can use MAKECMDGOALS to get the target: all clean: ifeq ($(MAKECMDGOALS), clean) @echo "This is an clean recipe" else @echo "This is not a clean recipe." endif $ make This is not a clean recipe. $ make clean This is an clean recipe


2

Then I'd like to append .o to each word. There is no need for the round trip through the shell. Make is powerful enough to provide helpers for common operations on file names like this. In your case you want the function with the self-explanatory name addsuffix: DEPENDENCIES = $(addsuffix .o, $(DEPENDENT_FILES)) Which gets you a.o b.o c.o for an input list ...


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You need to realize that for all the similarities in their syntaxes, make and shell are quite apart and have to be used with abundant caution. To make matters worse, make is very stingy with its warnings. You erred in two places in your make code: ## bad code DEPENDENCIES := $(echo '$DEPENDENT_FILES' | sed 's/\>/\.o/g') There is no GNU make built-in ...


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Functions always looked clearer to me then %: CLASS1=foo far CLASS2=boo bar define f $1/qux.json: $(wildcard $1/*.csv) $2 endef $(foreach i, $(CLASS1), $(eval $(call f, $i,my-script1.py -o $$@ $$^))) $(foreach i, $(CLASS2), $(eval $(call f, $i,my-script2.py -o $$@ $$^))) But really, writing the following takes less time: foo/qux.json: $(wildcard foo/*....


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