Questions tagged [gnu-make]
GNU Make is the GNU project's implementation of the `make` utility. On BSD systems, the GNU Make executable is sometimes called `gmake` to differentiate it from BSD Make.
81
questions
0
votes
0answers
24 views
Valid bash won't execute in make [duplicate]
# Makefile
test :
while true; do
echo test
done
test2 :
while true; do echo test; done
make test throws the error
while true; do
/bin/sh: -c: line 1: syntax error: unexpected ...
0
votes
1answer
40 views
How can I run make on file update?
I would like to be able to watch the files in my project and have make run every time one of the targets gets updated (unless it's changed by make itself I suppose). This is a common feature in many ...
0
votes
0answers
36 views
How do the two identical targets in a Makefile work?
I have a Makefile that has two identical targets, one for mkdir and the other for cp.
The Makefile creates dir when it does not exist, and then copy files. I wonder how it works. As I know, Makefile ...
2
votes
2answers
37 views
How do I build PKGCONF and LIBFFI and subsequently Python3.9 with ctypes support without sudo and write access to /usr/local?
The Question(s)
How do I properly configure pkgconf and libffi to allow the python3 build process to correctly use my libffi version at every step of the build process, in order to import the _ctypes ...
0
votes
1answer
33 views
Determining the type of makefile recipe
I want to determine the type of recipe the user entered in the shell. However the below code always return false .
all clean:
ifeq ("$@", "clean")
echo "This is an ...
0
votes
0answers
31 views
Makefile and lazy loading env file
What I want to do ?
Load an env file in "lazy" loading like this:
$ cat env.int
X=file
$ make toto
X=file
$ X=env make toto
X=env
What I got ?
I've got a env-file env.int like this:
X=file
...
1
vote
1answer
31 views
is there any way to skip a make's target?
I am trying to add a patch so that a software can compile and run correctly, unfortunately in order to add the change I am trying I always run into an annoying code style check error. Is there any way ...
-1
votes
1answer
43 views
How to introduce variables in Makefile
I'm using Bash on Ubuntu and GNU Make 4.2.1.
I'm trying to write a Makefile that would perform simple operations on some data (.TXT files) I have.
My different .TXT files are stored in 3 directories ...
0
votes
2answers
257 views
Variable not found in makefile recipe
why doesn't this simple recipe work ?
.PHONY: test
test:
foo := $(shell ls | grep makefile) ;\
echo $(foo)
results in
$> make test
makefile:65: warning: undefined variable 'foo'
foo := ...
0
votes
0answers
21 views
Induction in makefile
Can I make a recipe where a file named 3 has 2 as a prerequisite. 2 has 1 as a prerequisite. And 1 has no prerequisite?
Something like
1:
touch 1
n: n - 1
touch n
0
votes
1answer
101 views
Compiling drivers/staging
I need to compile all staging drivers. I am using make allyesconfig and I have also set CONFIG_BROKEN=y and CONFIG_COMPILE_TEST=y .
Right now, make modules C=1 M=drivers/staging prints MODPOST drivers/...
0
votes
1answer
393 views
What is the meaning of shell in $(shell uname -r)
I was reading a makefile where I found this statement
make -C /lib/modules/$(shell uname -r)/build/ M=$(PWD) modules
Can anyone explain what is shell here. Command substitution is being tried here ...
0
votes
1answer
54 views
Why is only the first prerequisite executed?
Here is the makefile.
.PHONY: all target1 target2 target
all: target1 target2
target1: NUM = 1
target2: NUM = 2
target1 target2: target
target:
@echo "this is target ${NUM}"
And the output is:
...
0
votes
0answers
79 views
Custom error message in GNU make if required but not otherwise?
In GNU's make is it possible to print a custom error message instead of GNU's default one, possibly with the line number as well? I am fine with make's default behavior in all other scenarios.
Here ...
0
votes
0answers
74 views
Use variables in Makefile recipe
Consider this Makefile:
DIRS = foo bar baz
ADIRSGLOBAL = $(addprefix A, $(DIRS))
all: $(DIRS)
$(DIRS):
ADIR=$(addprefix A, $@)
@echo $(addprefix A, $@)
@echo "ADIR="$(ADIR)
...
1
vote
0answers
23 views
Pattern-specific make variable based on the highest level target name
Goal
In the usual case of a target (mother target) calling another target (child target) as prerequisite, I'd like to assign a pattern-specific variable (see the manual page) with the following ...
1
vote
1answer
467 views
What's the difference between percent vs asterisk (star) makefile prerequisite
I'm trying to understand why some Makefiles have prerequisites with %.txt and others have *.txt.
I've created this folder layout.
$ tree .
.
āāā hi1.txt
āāā hi2.txt
āāā hi3.txt
āāā Makefile
First, ...
0
votes
1answer
12 views
Outputing the predefined variables `make -R` references?
According to the docs on make there is a -R switch,
-R, --no-builtin-variables
Don't define any built-in variables.
How can I find those builtin variables and their values?
1
vote
1answer
104 views
How to get the relative path between two directories?
Say I have a variable with a path release/linux/x86, and want the relative path from a different directory (i.e. ../../.. for current working directory), how would I get that in a shell command (or ...
2
votes
2answers
1k views
“Command not found” passing argument from Makefile to shell script
I have a info.properties file where I have this MY_NAME property and I can use this property on my Makefile. I already tried but I can't use that property directly on myScript.sh file.
So I'm trying ...
1
vote
1answer
436 views
Makefile - Set multiple variables on a single stage
I have this Makefile where I'm having some troubles on simply set some variables:
my_stage:
echo "FULL_NAME=$(FULL_NAME)"
echo "MY_NAME=$(MY_NAME)"
$(eval SOME_NAME=$(shell sh -c "...
0
votes
1answer
2k views
Simple shell loop fail in Makefile
Why does the shell loop
l='abc de f'; for k in $l ;{ echo $k; }
inside Makefile not work ?
instead only give
abc de f
at once
How to solve such in the definitive way?
-1
votes
1answer
26 views
Makefile not linking required dependency
The two target executables are made successfully at first:
$ rm build/* bin/*
$ make
g++ -Wall -g -c -o build/Person.o src/Person.cpp
g++ -Wall -g -c -o build/PersonTests.o test/PersonTests.cpp
g++ -...
1
vote
1answer
35 views
How do I get Make to acknowledge two intermediate dependencies from one recipe?
I am converting .sup files to .ass files using the following recipes:
%.idx %.sub: %.sup
bdsup2subpp --language en -o $*.sub $<
%.srt: %.sub
vobsub2srt $*
%.ass: %.srt
ffmpeg -...
3
votes
3answers
294 views
What is “sed -i 's,-m64,,g'” doing to this Makefile?
What is the meaning of sed command sed -i 's,-m64,,g' Makefile?
Does it simply remove -m64 argument from Makefile?
Is it the same with sed -i 's/-m64//g' Makefile,
just use / delimiter in place of ...
2
votes
1answer
142 views
alternatives to using make as a script runner [closed]
tl;dr
make is working for me, but I'm looking for the appropriate tool.
I'm currently using Makefiles as script runners for my projects. In order to standardize each project, I just create a makefile ...
0
votes
1answer
425 views
Process continues to run after receiving uncaught SIGINT (Ctrl-C from terminal)
I am trying to interrupt some running processes with Ctrl-C from the terminal in Centos7; some do, some don't.
One of the problematic processes (Process-A) is a GNU makefile with nothing fancy; just ...
11
votes
1answer
16k views
Makefile: Default Value of Variable that is set but has null value
I have a Makefile that has a variable that needs to have a default value in case when variable is unset or if set but has null value.
How can I achieve this?
I need this, as I invoke make inside a ...
4
votes
1answer
2k views
Make - How to suppress make error messages without suppressing other output
I'm implementing a simple build system that's actually just a wrapper around Make. Since this build system already emits its own error messages, I don't want Make to produce error messages like
make: ...
2
votes
2answers
1k views
Why don't here strings in Makefiles using Bash work?
I just solved a problem with my Makefile(s). Make trips over every <<< with the error message
/bin/sh: 1: Syntax error: redirection unexpected
And I would like to know why. (I am using Bash ...
5
votes
3answers
5k views
How can I partially serialize with GNU make
When I have a make task where a specific target needs to be made before another, while in parallel mode, this is simple when using SunPro Make (dmake). The following makefile:
install: dir dir/file
...
11
votes
2answers
2k views
How can I use files from HTTP as prerequisites in GNU make?
I want to use files from the World Wide Web as prerequisites in my makefiles:
local.dat: http://example.org/example.gz
curl -s $< | gzip -d | transmogrify >$@
I only want to "transmogrify" ...
0
votes
1answer
87 views
Why does GNU make's eval convert a list to a scalar?
I'm trying to to use eval to define a few make variables, but implicitly it seems to convert a list into a scalar. I can't seem to figure out how to avoid this behavior. Here's my current Makefile:
...
2
votes
0answers
760 views
Is there an automatic translator from Makefile to CMakeLists.txt?
I have several inherited projects - on RHEL 7, part of which are created using make, and the rest are utilising cmake.
I'm wondering: is there an automatic translator that will take a Makefile as ...
-1
votes
1answer
3k views
What does exactly does GNU make dep do?
I am trying to understand GNU Make and trying to understand some c code and GNU autotools.
There's a folder let's say lib, with three subfolders and a makefile.
lib
...libA
...---compile.sh
...---...
8
votes
1answer
2k views
Visualizing dependencies coded up in makefiles as a graph
Closely related to How to display dependencies given in a makefile as a tree? But the answers given there is not satisfactory (does not work).
Is there a tool to visualize the Directed Acylic Graphs (...
1
vote
2answers
2k views
Makefile, sqare brackets built-in, variable expansion and command substitution
To embrace the DRY (Donāt Repeat Yourself) principle, I sometimes need to share pieces of shell commands in a Makefile. So there is a recipe somewhere in that file like:
shell=/bin/bash
# ā¦
.ONESHELL:...
1
vote
1answer
2k views
GNU make - How to concatenate to variable depending on shell command result (GCC version)?
I want to add another option to the CFLAGS make variable, depending on the result of a shell command that i want to execute outside of a recipe in my "configuration" section of the makefile. This is ...
0
votes
1answer
82 views
How can I refactor this Makefile to not use fake .out outputs?
I have tests in tests/FILENAME-test.sh and for each one I want to run the script inside a docker container.
How can I refactor this Makefile to not use TEST_OUTPUTS like I have?
Also, how can I make ...
3
votes
1answer
1k views
Why does make behave strangely when writing multiple targets using the % character?
According to GNU Make Manual
A rule with multiple targets is equivalent to writing many rules, each with one target, and all identical aside from that. The same recipe applies to all the targets, ...
7
votes
2answers
6k views
gnuMake, How to have an environment variable override
Currently I am working with Makefiles that have definitions like
MYLIB=/.../mylib-1.2.34
The problem is that these are different for different developers, and it is a pain having to re-edit the file ...
1
vote
0answers
234 views
Compiling Octave: how to add a new item to the include directories for Qt?
Situation
My distro is Ubuntu 14.04. I am installing Octave 4.2.1. I have a shell script doing this for me using GNU make.
Octave is in search of Qt libraries. I wish to use the Qt5 5.8 binaries ...
1
vote
0answers
326 views
PHP 7.1.2 cannot Gmake : Zend Error
I use Solaris 11.3 Sparc 64 bit, Mysql Enterprise Advance 5.7.1, Apache 2.4.25 and PHP 7.1.2
I configure PHP with following parameter.
export CC="gcc -m64"
export CFLAGS="-std=gnu99"
./configure --...
14
votes
2answers
25k views
What does % symbol in Makefile mean
I am playing around with makefiles and I came across %.o or %.c. From what I understood, it specify all c or o files. But why this work:
%.o: %.c
$(CC) -c $^ -o $@
and this doesn't work
...
3
votes
1answer
3k views
gcc compiles gcc with errors 'template with C linkage' and 'template specialization with C linkage'
I am working with Ubuntu 14.04 LTS.
This already ships a packaged gcc 4.8.4 but I wanted to have a later version of gcc.
Using the existing version 4.8.4, I built version 4.9.4 from the source code ...
0
votes
1answer
374 views
Make pattern match directories
I'm using gnu make and stow to manage some configurations (dotfiles).
I have multiple directories in my repo:
dotfiles/
āāā Makefile
āāā package1/
āāā package2/
Currently, my Makefile looks like:
...
2
votes
0answers
104 views
How to check if a target will be run?
I know that the variable MAKECMDGOALS In GNU Make will contain the names of final goals for the run, i.e. the targets included on the command line.
However I'd like to check if a target will be made, ...
42
votes
1answer
4k views
How does this Makefile makes C program without even specifying a compiler?
I was using a Makefile from the book "Advanced Linux Programming (2001)" [code]. It was strange for me to see that GNU make does compile the code correctly, without even specifying a compiler in the ...
1
vote
1answer
596 views
apply rules in a list of files in GNU Make (or 'for' instruction in GNU Make)
I have this rules in my GNU Makefile:
FITXER = fitxa.md
$(FITXER).html: $(FITXER)
pandoc --from markdown --to html $(FITXER) -o $(FITXER).html
$(FITXER).jpeg: $(FITXER).html
wkhtmltoimage $(...
7
votes
3answers
8k views
Using wildcard in GNU Make pattern rule
Assume doc.pdf is the target.
The following rule triggers a regeneration of doc.pdf whenever doc.refer is updated, but is also happy when doc.refer does not exist at all:
doc.pdf: doc.mom $(wildcard ...
