0

The core number is 0,4,8,.....39 in the sensors command.

Why not 0,1,2,3,4.....?

foo@foo-linux:~$ sensors
coretemp-isa-0000
Adapter: ISA adapter
Package id 0:  +73.0°C  (high = +80.0°C, crit = +100.0°C)
Core 0:        +46.0°C  (high = +80.0°C, crit = +100.0°C)
Core 4:        +50.0°C  (high = +80.0°C, crit = +100.0°C)
Core 8:        +52.0°C  (high = +80.0°C, crit = +100.0°C)
Core 12:       +47.0°C  (high = +80.0°C, crit = +100.0°C)
Core 16:       +73.0°C  (high = +80.0°C, crit = +100.0°C)
Core 20:       +50.0°C  (high = +80.0°C, crit = +100.0°C)
Core 24:       +58.0°C  (high = +80.0°C, crit = +100.0°C)
Core 28:       +52.0°C  (high = +80.0°C, crit = +100.0°C)
Core 36:       +48.0°C  (high = +80.0°C, crit = +100.0°C)
Core 37:       +48.0°C  (high = +80.0°C, crit = +100.0°C)
Core 38:       +48.0°C  (high = +80.0°C, crit = +100.0°C)
Core 39:       +48.0°C  (high = +80.0°C, crit = +100.0°C)

update again

This is a 12th Gen Intel(R) Core(TM) i7-12700

This is a PC, not a server, with only 1 CPU socket.

update

foo@foo-linux:~$ cat /proc/cpuinfo | grep -i apicid
apicid      : 0
initial apicid  : 0
apicid      : 1
initial apicid  : 1
apicid      : 8
initial apicid  : 8
apicid      : 9
initial apicid  : 9
apicid      : 16
initial apicid  : 16
apicid      : 17
initial apicid  : 17
apicid      : 24
initial apicid  : 24
apicid      : 25
initial apicid  : 25
apicid      : 32
initial apicid  : 32
apicid      : 33
initial apicid  : 33
apicid      : 40
initial apicid  : 40
apicid      : 41
initial apicid  : 41
apicid      : 48
initial apicid  : 48
apicid      : 49
initial apicid  : 49
apicid      : 56
initial apicid  : 56
apicid      : 57
initial apicid  : 57
apicid      : 72
initial apicid  : 72
apicid      : 74
initial apicid  : 74
apicid      : 76
initial apicid  : 76
apicid      : 78
initial apicid  : 78
3
  • Related: Understanding core IDs. Mar 23, 2023 at 8:45
  • The processor number in /proc/cpuinfo is consecutive.
    – Mark K
    Mar 24, 2023 at 1:15
  • update the command result in question.
    – Mark K
    Mar 26, 2023 at 5:03

2 Answers 2

1

The core number comes from the cpu_core_id variable in the struct temp_data in the coretemp driver module. In its source code, cpu_core_id is described like this:

* @cpu_core_id: The CPU Core from which temperature values should be read
*       This value is passed as "id" field to rdmsr/wrmsr functions.

The rdmsr and wrmsr are machine code instructions to read/write Model-Specific Registers in the specified processor. The coretemp module uses these instructions through functions defined in arch/x86/lib/msr-smp.c. These functions just pass the CPU/core ID field through as-is, so the IDs shown are exactly the IDs used by your motherboard and CPU(s).

If your motherboard had 4 CPU sockets with only one socket populated, the firmware might have configured to assign the ID numbers to each socket in turn, so the IDs that would belong to the empty sockets are just left unused. But in your case, there is a sequence of four contiguous core IDs at the end (36 .. 39), so this might be something different.

Maybe this is a single processor which has two types of cores, and one type of cores is numbered with gaps in the numbering (0, 4, 8 ...) and the other type with no gaps (36 .. 39)?

To know more, it would be necessary to identify the exact processor model (e.g. using the output of lscpu | head -14), and then study the technical documentation of that processor model to see how the core IDs are assigned at the hardware/microcode level.

If the motherboard/firmware cannot dictate the assignment of core IDs, then one could guess that the CPU manufacturer might be planning a next generation of processors with more cores of the first type (i.e. with the gaps in the numbering either partially or completely filled). But this is just a guess, and the manufacturer's plans might change anyway...

1

This answer might not surprise you, but: because that's the way sensors was written.

sensors just uses sensors_get_detected_chips to walk through all the sensors there are – not through the CPU cores. And these order of the sensors is "as detected" on relevant buses (so, mainly I²C/SMBUS, emulated ISA), not in order of the (relatively arbitrary) numbering of CPU cores.

1
  • The question was not about separate sensor drivers, but about specifically how the coretemp driver gets its core IDs... but the answer is essentially the same: the IDs seem to be exactly what is used by the processor at the hardware/microcode level. One would have to study the technical documentation of that particular CPU model to know more.
    – telcoM
    Mar 23, 2023 at 11:48

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