How does MMU find out what address it should translate?

Question

When we try to read/write some data to/from a specific address we must know where the first page directory is stored and the address we want translate.

As for the first page directory (as far as I know linux uses 4-level paging, so the first one should be PGD), and for Intel - CR3 register will contain the address of PGD, but where the virtual address is stored? How will MMU understand that it should translate exactly this or that address?

UPD: I think I should clarify my question and provide a few details how I see that:

As I understood, when some virtual address's gonna be translated we have next steps:

1. Check the TLB.
2. If TLB hits then we have physical address (PA)
3. If it does not, we have to process translation fault
4. During translation fault we have to walk through software page tables to find the PA.
5. Here have to switch to kernel mode. (Btw, I know that usually kernel page tables and user page tables are the same, the difference is only in privileges, so is there a way that we won't switch to kernel mode?)
6. Then we're gonna set CR3 register to PGD address (or another top level page directory)
7. Now that's our work to walk through this table or not? If software should do it on its own then we know that VA (Virtual Address) within some var and can look for PA in page tables??? Or this work on MMU (or like smth that) and it will go through these tables and as for CR3 will know where the PGD, but how it can understand what address this is translating? Is it in some register or already loaded somewhere in memory?

Thank you for your time!

Answer 1

The steps you’ve listed aren’t quite right; hopefully fixing that will allow you to understand what’s going on.

0. The CPU attempts to access memory (e.g. to read an instruction, or because the current instruction accesses memory) — this is where the virtual address comes from.

1. Check the TLB.

2. If the TLB has an entry for the virtual address, we’ve got the corresponding physical address.

3. Otherwise, the MMU has to handle the TLB miss (it’s not a fault on x86; it gets counted but the kernel isn’t aware of it).

4. The MMU walks through the pages tables, potentially starting at the value stored in CR3. It knows the virtual address it needs to resolve, from step 0.

5. There’s no switch to kernel mode, this is all handled by the MMU (on x86).

6. CR3 and the page tables had to be set up before the memory access, nothing is changed here. (See this in-depth analysis of pagewalk coherence.)

Some architectures (MIPS, I think) do involve the kernel when handling a TLB miss; in such cases the virtual address which needs to be handled is provided in the fault information.