Despite having a data bus size of 64 bit, the address bus size of modern AMD64-compatible CPUs is/was 48 bit for some time which allows using 48-bit long virtual memory addresses with a maximum of addressable virtual memory of 2^48 => 256 TB.
Intel says  that since the Ice Lake CPU architecture, their CPUs support 5-Level Paging with 57-bit long virtual memory addresses. Linux supports this since Kernel 4.14 .
Does this mean that CPUs that support 5-Level Paging with 57-bit long virtual memory addresses implement a 57-bit long address bus?
The background of my question is that around 10-15 years ago, it was not a problem to learn about the address bus and data bus size of modern CPUs, but since approximately ten years, it is not simple to find information about the address bus size.