Makefile: how to sed correctly to edit a variable

Question

I'm trying to write a custom Makefile in which I collect all source files to compile against the main. First I collect their names:

# other sources to compile against (without extensions, separated by spaces)
DEPENDENT_FILES = greet farewell

Then I'd like to append .o to each word. In a shell, I can do this in many ways, e.g.

echo '$DEPENDENT_FILES' | sed 's/\>/\.o/g' # but I know, it's UNIX dependant
# or ...
echo '$DEPENDENT_FILES' | sed 's/[^ ]*/&\.o/g'

both result in greet.o farewell.o on the terminal, but fail (resulting in empty strings) during the make process. I write them as

DEPENDENCIES := $(echo '$DEPENDENT_FILES' | sed 's/\>/\.o/g')
# or ...
DEPENDENCIES := $(echo '$DEPENDENT_FILES' | sed 's/[^ ]*/&\.o/g')
# but they result in
$(info DEPENDENCIES is $(DEPENDENCIES)) # "DEPENDENCIES is "

I don't know what I'm doing wrong here, I suspect it could be something related to echos or pipes in Makefiles but I can't figure it out.

Please, I'd prefer answers related to working sed and echo solutions, without proposing different approaches: it's not the first time that I'm facing problems with echo and pipes in Makefiles and I still don't know what is wrong in my approach.

Answer 1

You need to realize that for all the similarities in their syntaxes, make and shell are quite apart and have to be used with abundant caution. To make matters worse, make is very stingy with its warnings.

You erred in two places in your make code:

## bad code 
DEPENDENCIES := $(echo '$DEPENDENT_FILES' | sed 's/\>/\.o/g')

• There is no GNU make built-in function named echo l, coz that is how make is understanding it to mean.
• What you need to do when you need to run an external utility is to call the gnu make built-in $(shell ...) function.
• Now there's an insidious issue lurking in the way you wrote the make code, and that is the variable $DEPENDENT_FILES. make will parse it as a make variable $D followed by a string literal EPENDENT ! This is coz make vars when not enclosed parentheses or braces are single letter only, rest being taken as literal string.
• Note shell vars vegin with $$ unless the eval is in play.

Answer 2

Then I'd like to append .o to each word.

There is no need for the round trip through the shell. Make is powerful enough to provide helpers for common operations on file names like this. In your case you want the function with the self-explanatory name addsuffix:

DEPENDENCIES = $(addsuffix .o, $(DEPENDENT_FILES))

Which gets you a.o b.o c.o for an input list a b c. A more complete example:

units = a b c

inc = $(addsuffix .h,$(units))
obj = $(addsuffix .o,$(units))

myprog: $(obj)
    gcc -o $@ $(obj)

header-bundle.h: $(inc)
    cat $< >$@

If you need more intricate substitutions, there’s also a variety of generic string operations but where they are sufficient, the file ops are more convenient and IMO easier to understand by a humble human.