I am trying to use yocto poky environment. I did the following:

#source environment-setup-cortexa9hf-neon-poky-linux-gnueabi 

Now, if I try to compile the program using:

#$(CC) hello.c -o hello.elf 

it throws me error since $(CC) isn't defined.

However, if I do $CC it works. I am confused on what is the fundamental difference between $(CC) and $CC?


3 Answers 3


I'm assuming that you've seen $(CC) in a Makefile where it serves as an expansion of the variable CC, which normally holds the name of the C compiler. The $(...) syntax for variable expansions in Makefiles is used whenever a variable with a multi-character name is expanded, as $CC would otherwise expand to the value of the variable C followed by a literal C ($CC would in effect be the same as $(C)C in a Makefile).

In the shell though, due to having a different syntax, $(CC) is a command substitution that would be replaced by the output of running the command CC. If there is no such command on your system, you would see a "command not found" error.

It's also possible that you've mistaken $(CC) for ${CC} which, in the shell, is equivalent to $CC under most circumstances. The curly braces are only needed if the variable's expansion is followed immediately by some other string that would otherwise be interpreted as part of the variable's name. An example of the difference may be seen in "$CC_hello" (expands the variable called CC_hello) and "${CC}_hello" (expands the variable CC and appends the string _hello to its value). In all other circumstances, ${CC} is equivalent to $CC. Note that using curly braces is not quoting the expansion, i.e. ${CC} is not the same as "$CC".

If have a shell or environment variable holding the name of the compiler that you're using for compiling C code, and you want to use that variable on the command line, then use "$CC", or just $CC if the variable's value does not contain spaces or shell globbing characters.

$CC -o hello.elf hello.c
  • 2
    Of course, by its nature you don't know if $CC will have spaces in its expansion, so you virtually always want "$CC".
    – chepner
    Mar 18, 2020 at 18:44

The two are not equivalent. In a line that contains $(foo), the $(foo) is replaced with the output of the command foo. For example:

$ echo "hello $(echo world)"
hello world

In a line that contains $foo, the $foo is replaced with the value of the variable named foo. For example:

$ foo=world
$ echo "hello $foo"
hello world
  • 6
    They may have seen $(CC) in a Makefile...
    – Kusalananda
    Mar 18, 2020 at 6:13
  • Not necessarily environment variable.
    – vonbrand
    Mar 22, 2020 at 20:38

This answer does not consider makefile syntax.

"$(CC)" is the output of the command CC.

"$CC" is the value of the variable CC.

This should make the difference clear:

$ CC=ls
$ echo $(CC)
CC: command not found
$ echo $CC


$ echo $($CC)
bin   cdrom  dev  home        initrd.img.old  lost+found  mnt  proc  run ...

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