1.) The chipset has been designed to split the memory-mapped I/O allocation of the audio controller into several blocks, and the base address for each block can be assigned separately. This results in a more flexible chipset design that can be configured to accomodate various different hardware configurations.
2.) The two blocks are not copies of each other, but are used for different purposes. To understand more, you'll have to download the datasheet PDF(s) for your chipset from Intel, and possibly also some documentation on the HD Audio standard, and then read some very solid technical documentation.
3.) If the audio controller needs a total of 1040K of address space for its MMIO functionality, assigning it in two separate blocks that are both power-of-2 sized, the firmware will have a higher chance of being able to assign all the MMIO areas of the various hardware components into one or just a few contiguous blocks of addresses, without leaving too many inconvenient "holes" of memory or unusable address space in between them. This allows the hardware memory management unit of the processor to work more efficiently, as the Memory Type Range Registers (MTRRs) can assign optimal access strategies for both MMIO and regular memory blocks. There is only a limited number of MTRRs available, so achieving a tight packing of MMIO blocks helps.
