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the x86_64 architecture allows 32-bit code run natively while operating in Long mode. Therefore a submode called "compatibility mode" was added. Now the the memory managment mode goes through the following tables to calculate physical address:

PML4 (Linux: PGD) -> PDPT (Linux: PUD) -> PD (Linux: PMD) -> PT -> physical page

Each of the tables mentioned above consists of 512 entries with the size of 64 bit, so you need 9 bit as an index for each table and 12 bit as an offset that is added to tha last address retrieved from PT. This sums up to 48 bit. Now it seems pretty clear that you can't achive the same with an 32-bit address.
Others already tried to explain how this is done (here or here) but in my opinion this can't be right. There it is explained that the PDPT and the PD only have one entry each but this behavior would cause some trouble in the way I understand it.
The MMU would take the first most significant 9 bits from the address to get the address for the PDPT. Now in the PDPT there is only one entry but the MMU has a strict procedure and will take the next 9 bits from the address as the index. Now in only one from 512 cases the fist entry would be selected. The same problem exists for the PD.
And that is not the only problem I see. As already stated 32 bit are not enough for a complete translation, so some tables have to be skipped somehow.

Hopefully I could explain my problem und someone can help me.

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The Compatibility sub-mode of the Long Mode in x86-64 does not affect paging, which functions as in 64-bit Long Mode. 32 implicit zero bits are inserted in bit positions 63-32 of the virtual address that is fed into the paging unit. You only need to set up page tables that map these zero bits to something valid, like the answer in the first question you linked to explained. See 2.1.4.1 Long-Mode Memory Management (PDF) in AMD64 Architecture Programmer’s Manual Volume 1: Application Programming

  • Perfect, thanks. – blackdog Jun 20 at 22:00

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