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I am using a LVDS display on an i.MX6 DualLite. The panel is supposed to be running at a clock of 51.2MHz. I am in the process of updating to a newer Yocto (Pyro) built BSP running 4.14.16. The older BSP is running 3.14.28 and was provided by the board vendor. The old BSP didn't implement the display in the clock tree, they wrote code that manually set the registers in the i.MX to setup the clocks. I am trying to avoid that, it seems like bad practice for something that should be set from the device tree.

My current device tree is:

panel {
    compatible = "ampire,tft-1024600-80-2", "panel-lvds";
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_panel>;
    backlight = <&backlight_lvds>;
    width-mm = <223>;
    height-mm = <125>;
    data-mapping = "vesa-24";
    enable-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;

    panel-timing {
        /* 1024x600 @60Hz */
        clock-frequency = <51200000>;
        hactive = <1024>;
        vactive = <600>;
        hsync-len = <16>;
        hfront-porch = <64>;
        hback-porch = <64>;
        vsync-len = <8>;
        vfront-porch = <8>;
        vback-porch = <8>;
        hsync-active = <0>;
        vsync-active = <0>;
        de-active = <0>;
        pixelclk-active = <0>;
        assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO>;
    };

    port {
        panel_in: endpoint {
            remote-endpoint = <&lvds1_out>;
        };
    };
};

The assigned-clock-parents was an attempt to make it similar to the old device tree and to get it on the pll5 portion of the tree. Even with that in there though (it made no difference in the clock output), I am seeing the following if I dump the debugFS clk_summary file (irrelevant portions removed):

   clock                         enable_cnt  prepare_cnt        rate   accuracy   phase
----------------------------------------------------------------------------------------
 osc                                      6            6    24000000          0 0
    pll5                                  0            0   296600000          0 0
       pll5_bypass                        0            0   296600000          0 0
          pll5_video                      0            0   296600000          0 0
             pll5_post_div                0            0    74150000          0 0
                pll5_video_div            0            0    74150000          0 0
                    ...
    pll2                                  1            1   528000000          0 0
       pll2_bypass                        1            1   528000000          0 0
          pll2_bus                        2            2   528000000          0 0
             pll2_pfd2_396m               6            6   396000000          0 0
                periph2_pre               1            1   396000000          0 0
                   periph2                1            1   396000000          0 0
                      mmdc_ch1_axi_podf   1            1   198000000          0 0
                         mmdc_ch1_axi     1            1   198000000          0 0
                            ldb_di0_sel   0            0   198000000          0 0
                               ldb_di0_div_3_5    0            0    56571428          0 0
                                  ldb_di0_podf    0            0    28285714          0 0
                                     ldb_di0      0            0    28285714          0 0
                            ldb_di1_sel           1            1   198000000          0 0
                               ldb_di1_div_3_5    1            1    56571428          0 0
                                  ldb_di1_podf    1            1    28285714          0 0
                                     ldb_di1      1            1    28285714          0 0
                                        ipu1_di0_sel  1            1    28285714          0 0
                                           ipu1_di0   1            1    28285714          0 0

This is what I see in the old BSP for clocks:

 clock                        enable_cnt  prepare_cnt  rate        accuracy
---------------------------------------------------------------------------------
 osc                            6           6            24000000   0
    pll5_bypass_src             1           1            24000000   0
       pll5                     1           1            716889600  0
          pll5_bypass           1           1            716889600  0
             pll5_video         1           1            716889600  0
                pll5_post_div   1           1            358444800  0
                   pll5_video_div 1           1            358444800  0
                      ldb_di1_sel 1           1            358444800  0
                         ldb_di1_div_7 1           1            51206400   0
                            ldb_di1_div_sel 1           1            51206400   0
                               ldb_di1 1           1            51206400   0
                                  ipu1_di1_sel 1           1            51206400   0
                                     ipu1_di1 1           1            51206400   0
                                        ipu1_pclk1_sel 1           1            51206400   0
                                           ipu1_pclk1_div 1           1            51206400   0
                                              ipu1_pclk_1     1           1            51206400   0

Is there a way to replicate the tree structure in the device tree? There is nothing else on pll5, so I am not worried about breaking something else.

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