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Operating System Concepts says:

During I/O, the various device controllers raise interrupts when they are ready for service. These interrupts signify

  • that output has completed, or
  • that input data are available, or
  • that a failure has been detected.

Are interrupts used to signify that output is ready or input has completed?

If not, do they need to be signified by some other way?

Thanks.

  • 1
    You reference a source that says that interrupts signify "output has completed", and you ask about "output is ready". In the context of your question, what does "ready" mean, and how does that differ from "completed"? – Andy Dalton Oct 1 '18 at 15:05
  • I guess "output is ready" means that when CPU tells the device to output something, the device is busy, and can be ready to perform the output later – Tim Oct 1 '18 at 15:12
  • Ah, then I think that @AndrejaKo 's answer addresses your question well. – Andy Dalton Oct 1 '18 at 15:14
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that output has completed, or

Are interrupts [also] used to signify that output is ready?

Yes.

Consider writing to a serial port device. The device has a receive buffer called a FIFO, to store a small amount of data e.g. 16 bytes.

There may be an interrupt both when

  1. the buffer falls empty, and output is complete. This is used to implement tcdrain() on Linux. Allegedly "this function should be used when changing parameters that affect output". E.g. when you want to change the "baud rate" (frequency) of the serial port, you can use this to wait until all buffered data has been transmitted using the current baud rate.
  2. a byte has been transmitted out from the buffer. There is now space available. The device is now ready for the CPU to push another byte in to the buffer.

that input data are available, or

Are interrupts [also] used to signify that input has completed?

Maybe. I'm not sure there's two different things here though, at least in my example.

Consider reading from a serial port device. The device has a transmit buffer called a FIFO, to store a small amount of data e.g. 16 bytes.

When the FIFO has collected at least one byte from the input, the device sends an interrupt. For example it may change from a low to a high voltage on a line connected to the CPU.

The CPU can consume bytes from the buffer, by reading from an IO port or from IO memory.

Sidenote: such transactions may be allowed to take longer than reading from system RAM. To allow this, the IO device must insert "wait states" on the bus. I.e. there is a brief handshake, where it may take several cycles of the bus frequency before the IO device sets a "data ready" bit. Wait states may equally be applied when writing to an IO port / IO memory. However, wait states are only used to cover a known difference in operation frequency/latency between different devices. They are not used to wait for external input or output. This is because they block the CPU from continuing and doing anything else.

So when input is available, an interrupt is signalled. If you like, you can say the input is "completed" when the CPU has read in the input byte. But no interrupt is required to signal this. Just as no interrupt is required to signal that a read from memory is complete.

A condition where the input buffer is full actually seems more like an error condition - it suggests a buffer overflow. That condition may indeed be recorded by the device, allowing the OS to detect the error. However, I don't think there is reason to send an interrupt specifically for overflow. Because the device could already have sent an interrupt when input became available.

5

It's a good thing you put or in the title, since the answer is yes.

Namely, exact answer depends on the exact interrupt you're asking about. Let's use an SPI port and DMA as an example. The SPI is a bidirectional serial interface.

It's common, for example, for DMA interrupts to mark so-called water levels. You'll have an interrupt when the DMA buffer is full, when it's "almost full" (say 3/4), when it's "almost empty" (say 1/4) and when it's completely empty.

For an SPI port, you'll have two DMA channels. One will handle the data coming in from the outside device, and another will handle data which is to be sent from your computer to the device.
So, when the output DMA channel interrupt indicates that the buffer is empty, that means that output has completed. When the input DMA channel interrupt indicates that the buffer is not empty, that means that that input data are available.

  • +1 for last two sentences and a nice concrete example. But I'm curious thinking about what cases your OS would actually want two different intermediate interrupts for the same buffer e.g. 3/4 and 1/4 on the same buffer. Is that common? – sourcejedi Oct 1 '18 at 16:07
  • @sourcejedi Unfortunately, I don't have enough experience to say if it's commonly used or not, but it is a feature that can be found in many processors/microcontrollers. – AndrejaKo Oct 1 '18 at 19:21
  • @sourcejedi As to when you'd use it, well let's say that you have serial buses of different speeds. If your drivers are set up properly, you can set up your DMA to have buffer level of around 50% when everything is fine. When the buffer goes above 75%, you could attempt to slow down the fast bus, and if the buffer goes down to 25%, you can try to increase the speed. Depending on how critical you are, you might try to have multiple buffers, and use the buffer full interrupt to switch to the DMA pointers to the new buffer, in order to prevent overflow. – AndrejaKo Oct 1 '18 at 19:33

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