35

You can see the output from lscpu command -

jack@042:~$ lscpu
Architecture:          x86_64
CPU op-mode(s):        32-bit, 64-bit
Byte Order:            Little Endian
CPU(s):                56
On-line CPU(s) list:   0-55
Thread(s) per core:    2
Core(s) per socket:    14
Socket(s):             2
NUMA node(s):          2
Vendor ID:             GenuineIntel
CPU family:            6
Model:                 79
Model name:            Intel(R) Xeon(R) CPU E5-2690 v4 @ 2.60GHz
Stepping:              1
CPU MHz:               2600.000
CPU max MHz:           2600.0000
CPU min MHz:           1200.0000
BogoMIPS:              5201.37
Virtualization:        VT-x
Hypervisor vendor:     vertical
Virtualization type:   full
L1d cache:             32K
L1i cache:             32K
L2 cache:              256K
L3 cache:              35840K
NUMA node0 CPU(s):     0-13,28-41
NUMA node1 CPU(s):     14-27,42-55

I can see that there are 2 sockets (which is like a processor ??) and inside each of the socket we have 14 cores. So, in total 2x14=28 physical cores. Normally, a CPU can contain multiple cores, so number of CPUs can never be smaller than number of Cores. But, as shown in the output CPUs(s): 56 and this is what is confusing me.

I can see that Thread(s) per core: 2, so these 28 cores can behave like 2x28=56 logical cores.

Question 1: What does this CPUs(s): 56 denote? Does CPU(s) denote number of Virtual/Logical core, as it cannot be a Physical core core atleast?

Question 2: What does this NUMA node mean? Does it represent the socket?

2 Answers 2

44

“CPU(s): 56” represents the number of logical cores, which equals “Thread(s) per core” × “Core(s) per socket” × “Socket(s)”. One socket is one physical CPU package (which occupies one socket on the motherboard); each socket hosts a number of physical cores, and each core can run one or more threads. In your case, you have two sockets, each containing a 14-core Xeon E5-2690 v4 CPU, and since that supports hyper-threading with two threads, each core can run two threads.

“NUMA node” represents the memory architecture; “NUMA” stands for “non-uniform memory architecture”. In your system, each socket is attached to certain DIMM slots, and each physical CPU package contains a memory controller which handles part of the total RAM. As a result, not all physical memory is equally accessible from all CPUs: one physical CPU can directly access the memory it controls, but has to go through the other physical CPU to access the rest of memory. In your system, logical cores 0–13 and 28–41 are in one NUMA node, the rest in the other. So yes, one NUMA node equals one socket, at least in typical multi-socket Xeon systems.

4
  • 1
    Stefan, in this en.wikipedia.org/wiki/Non-uniform_memory_access#/media/… (courtesy Wikipedia link you referred in your post) - Are there 2 NUMA nodes on each socket? As I understood, in this configuration, RAM is 32 GB and each Socket has 2 NUMA nodes, with each node being shared by 1 CPU Packages consisting of 8 processors, logical or otherwise. Am I correct? In my system, as you also mentioned, there is one NUMA node per socket (NUMA node0 CPU(s): 0-13,28-41). So, I suppose this pic is not an abstraction of the architecture of my system.??
    – cph_sto
    Sep 13, 2018 at 15:41
  • 4
    That image shows the NUMA architecture of a Bulldozer CPU; your Xeon CPU has a different architecture. NUMA layouts depend on the memory controllers, not the sockets (directly); you can have one memory controller per socket (as on current Xeon), multiple memory controllers per socket, or even external memory controller(s) instead. Sep 13, 2018 at 15:45
  • Very helpful answer, but sometimes there are "On-line CPU(s) list" and "Off-line CPU(s) list", I assume “Thread(s) per core” × “Core(s) per socket” × “Socket(s)”. equals to the number of On-line CPU(s) list, not CPU(s) line? Jan 26 at 2:26
  • @wjrforcyber “Thread(s) per core” × “Core(s) per socket” × “Socket(s)” describes the available hardware, and matches the “CPU(s)” line. Jan 26 at 13:13
1

An image to complement what Stephen said, modified from https://commons.wikimedia.org/wiki/File:Supermicro_dual_opteron_server_board_IMGP7335_wp.jpg[], your machine likely looks something like:

enter image description here

If you squint you can see "CPU1" and "CPU2" marked on the motherboard near each socket. We can also see the little lever used to hold each CPU in place, as demonstrated e.g. on this video: https://www.youtube.com/watch?v=Ng5D9T__4Jc

Dual socket motherboards are a very popular server motherboard architecture.

On the image we can also see 8 slots marked P1-DIMM1A, P1-DIMM1B, P1-DIMM2A, P1-DIMM2B, and similar for P2-*. DIMM is a generic name for this RAM memory form factor so we understand that these are memory slots, and presumably P1 and P2 mean "processor 1" and "processor 2", so these likely make up the two NUMA nodes lscpu would be talking about.

And now for the grand finale, some ASCII art:

+--------------------------+   +--------------------------+
| Socket 1                 |   | Socket 2                 |
|                          |   |                          |
| +----------------------+ |   | +----------------------+ |
| |  Core 0              | |   | |  Core 0              | |
| | +------------------+ | |   | | +------------------+ | |
| | | Thread 0 (cpu0)  | | |   | | | Thread 0 (cpu15) | | |
| | +------------------+ | |   | | +------------------+ | |
| | | Thread 1 (cpu1)  | | |   | | | Thread 1 (cpu16) | | |
| | +------------------+ | |   | | +------------------+ | |
| +----------------------+ |   | +----------------------+ |
|                          |   |                          |
| +----------------------+ |   | +----------------------+ |
| |  Core 1              | |   | |  Core 1              | |
| | +------------------+ | |   | | +------------------+ | |
| | | Thread 0 (cpu2)  | | |   | | | Thread 0 (cpu17) | | |
| | +------------------+ | |   | | +------------------+ | |
| | | Thread 1 (cpu3)  | | |   | | | Thread 1 (cpu18) | | |
| | +------------------+ | |   | | +------------------+ | |
| +----------------------+ |   | +----------------------+ |
|                          |   |                          |
|                          |   |                          |
  .... more cores .....          .... more cores .....
|                          |   |                          |
| +----------------------+ |   | +----------------------+ |
| |  Core 6              | |   | |  Core 6              | |
| | +------------------+ | |   | | +------------------+ | |
| | | Thread 0 (cpu12) | | |   | | | Thread 0 (cpu26) | | |
| | +------------------+ | |   | | +------------------+ | |
| | | Thread 1 (cpu13) | | |   | | | Thread 1 (cpu27) | | |
| | +------------------+ | |   | | +------------------+ | |
| +----------------------+ |   | +----------------------+ |
|                          |   |                          |
| +----------------------+ |   | +----------------------+ |
| |  Core 7              | |   | |  Core 7              | |
| | +------------------+ | |   | | +------------------+ | |
| | | Thread 0 (cpu28) | | |   | | | Thread 0 (cpu42) | | |
| | +------------------+ | |   | | +------------------+ | |
| | | Thread 1 (cpu29) | | |   | | | Thread 1 (cpu43) | | |
| | +------------------+ | |   | | +------------------+ | |
| +----------------------+ |   | +----------------------+ |
|                          |   |                          |
  .... more cores .....          .... more cores .....
|                          |   |                          |
| +----------------------+ |   | +----------------------+ |
| |  Core 14             | |   | |  Core 14             | |
| | +------------------+ | |   | | +------------------+ | |
| | | Thread 0 (cpu40) | | |   | | | Thread 0 (cpu54) | | |
| | +------------------+ | |   | | +------------------+ | |
| | | Thread 1 (cpu41) | | |   | | | Thread 1 (cpu55) | | |
| | +------------------+ | |   | | +------------------+ | |
| +----------------------+ |   | +----------------------+ |
|                          |   |                          |
+--------------------------+   +--------------------------+

where we can see how the logical core numbers (cpu0 - cpu55) might have been across each hyperthread of each core. It's a bit confusing that he Linux kernel calls them "CPUs" when they are just hyperthreads and not the actual chip. But it's also understandable why.

Related "hyperthreads vs cores" answer: So what are logical cpu cores (as opposed to physical cpu cores)?

1
  • 1
    Thanks a lot for your explanation.
    – cph_sto
    May 31, 2023 at 9:46

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