I have a 10G ethernet adapter from Intel with two ethernet ports (x550-T2) installed in PCIe port of a Xilinx FPGA board running petalinux. I am testing network bandwidth by running simultaneous iperf3 server-client connections on both 10G ports. But the bandwidth on 2x 10G link is same as 1x 10G link. The reason being that bottleneck is not on the link capacity, but rather, interrupt handling. Xilinx FPGA PCIe interface doesn't support Receiver side scaling (RSS), so all the interrupts are directed to CPU0, as a result of which, CPU0 is overloaded with interrupt handling. This is true, whether 1x or 2x 10G links are active. So I was wondering if it's possible to direct eth1 interrupts to CPU0 and eth2 interrupts to CPU1, so that at least I can see some increase in network bandwidth when I go from 1x to 2x 10G links.