Hyperthread and processors Clock, Size, and Capacity

Question

When I enable hyperthreading, CPU size and capacity decrease to about half the non-hyperthreaded value. Since most of my processes use only two cores, should I disable hyperthreading?

lshw -C processor (cpu:0 and cpu:1 show the same results)

Hyperthread ON

*-cpu:0                   
   description: CPU  
   product: Intel(R) Xeon(R) CPU           X5690  @ 3.47GHz  
   vendor: Intel Corp.  
   physical id: 5  
   bus info: cpu@0  
   version: Intel(R) Xeon(R) CPU X5690 @ 3.47GHz  
   slot: CPU0 PROCESSOR  
   size: 1596MHz  
   capacity: 1596MHz  
   width: 64 bits  
   clock: 2105MHz  
   capabilities: x86-64 fpu fpu_exception wp vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 popcnt aes lahf_lm ida arat epb tpr_shadow vnmi flexpriority ept vpid cpufreq  
   configuration: cores=6 enabledcores=6 threads=12  

Hyperthread OFF

*-cpu:0                   
   description: CPU  
   product: Intel(R) Xeon(R) CPU           X5690  @ 3.47GHz  
   vendor: Intel Corp.  
   physical id: 5  
   bus info: cpu@0  
   version: Intel(R) Xeon(R) CPU X5690 @ 3.47GHz  
   slot: CPU0 PROCESSOR  
   size: 3459MHz  
   capacity: 3459MHz  
   width: 64 bits  
   clock: 2105MHz  
   capabilities: x86-64 fpu fpu_exception wp vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm dca sse4_1 sse4_2 popcnt aes lahf_lm ida arat epb tpr_shadow vnmi flexpriority ept vpid cpufreq  
   configuration: cores=6 enabledcores=6 threads=6  

Answer 1

Good question and interesting command. What is this? Debian?

However I looked up the meaning of "size" on the home-page for the command lshw.

So basically this shows how HT works: Instead of just one internal CPU-command-pipeline, you get two pipelines with half the clock-rate.

Half the clock-rate is propably well enough to be constantly fed to - but the processor can do its work on both pipelines simultaniously.

Conclusion: HT is ok, since it can utilize the CPUs internal capabilities to its fullest. Apart from that CPUs are propably never the bottleneck nowadays.

You would need code that resides in the CPU-cache that gets executed without being swapped out to take advantage of the full CPU-speed - and even then the result has to be written to somewhere - RAM-throughput will be propably smaller than the CPU-througput any way.