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I wonder why 'Makefile' demands dependency line in spite of a command line already has list of file. For example,

hello : main.o hello.o

        gcc -o main.o hello.o

The gcc command already contains main.o, hello.o. Writing dependency line looks inefficient.

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    I'm feeling you may have missed the point of make somewhat: it's primary advantage isn't just to blindly run a set of commands (shell scripts are perfectly good at that), but to work out which commands need to be run. It can't do that without dependencies. – Philip Kendall Feb 11 '17 at 14:30
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Yes, but it's the build rule that is unnecessary, not the dependency. It the dependencies that makes make tick, after all. The rule for building is also seriously wrong (will overwrite main.o rather than building hello).

Using the implicit rules, this may be shortened to just

hello: main.o hello.o

Or if you want an explicit make rule in addition to the dependency:

hello: main.o hello.o
    $(CC) -o $@ $<

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