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Is it possible to disable L1 and/or L2 cache on Ubuntu 14.04 (preferably in a higher level language like Python)? If so, how?

In addition, will disabling the cache differ significantly between different architectures? If so, I'm more interested in an ARM Cortex-A15.

EDIT

While researching how to disable the cache, I did find out about the "drop_caches" file in /proc/sys/vm/ from the kernel.org documentation

"Writing to this will cause the kernel to drop clean caches, as well as reclaimable slab objects like dentries and inodes. Once dropped, their memory becomes free."

...

"This file is not a means to control the growth of the various kernel caches (inodes, dentries, pagecache, etc...) These objects are automatically reclaimed by the kernel when memory is needed elsewhere on the system."

This does not seem like what I'm looking for as not only does this not seem like it would disable the cache, I thought that virtual memory resides within the operating system and not on the hardware. My goal is to disable the cache so the desired memory must be sought elsewhere, such as within the RAM.

EDIT

To clarify, I understand what disabling the cache will do to the system. However, it is a common technique used in space applications to increase reliability for safety-critical applications. Here are some resources that document this phenomenon:

Reducing embedded software radiation-induced failures through cache memories

Guideline for Ground Radiation Testing of Microprocessors in the Space Radiation Environment

There are even books on the topic:

Ionizing Radiation Effects in Electronics: From Memories to Imagers

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  • If you are trying to do things like disabling cache, you are doing embedded programming, if you are doing embedded programming, you should probably be using an embedded language (C), and I wouldn't use an OS. As an aside disabling cache is going to hugely slow down your system. – Sam Oct 18 '16 at 22:42
  • I have other ways to speed up my system without cache, but I can't tell how effective these methods are until I disable the cache and run benchmarks. I am very much aware C or assembly is the preferred choice for embedded applications. However, there are several high level things happening that make more sense to do in Python. It'd just be more convenient if Python had support for doing something like disabling the cache for my particular application. As for stripping the OS, bare-metal is not an option for me unfortunately. – AustinTronics Oct 18 '16 at 23:18
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You can not do it directly in Python, as you need a kernel module to do that (and root rights to load that module).

See http://lxr.free-electrons.com/source/arch/arm/mm/cache-v7.S#L21 for what it takes to invalidate the L1 cache (invalidate, not disable).

Different CPU architectures (e.g x86 vs ARM) require different assembly code (CPU instructions) to disable the cache. I'm not sure if the Linux kernel has any possibility to disable the L1/L2/L3/L4 caches and if it would have that, I believe it would be just used internally for a short period of time, as the CPU is slow without these caches.

See Is there a way to disable CPU cache (L1/L2) on a Linux system? for a link on how you can disable the cache on an x86/x64 system (you need to change the register cr0). For ARM check Cache disabled behavior.

I'm not sure that you completely understand what the CPU caches do. Can you please elaborate why you want to cripple the performance of your system?

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  • The application is high-performance embedded computing for aerospace. Up-time is more important to my application than performance. I know this sounds strange, but the phenomenon is well documented. – AustinTronics Oct 18 '16 at 21:55
  • How can you have a "high-performance" application without a CPU cache? What do caches have to do with uptime? – tehnicaorg Oct 19 '16 at 12:35
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    I am a software developer in R&D, we do lots of crazy things. Sorry if it seems like I'm leaving out information or being vague throughout my responses, but I can't get into as much as I'd like since it is propriety information. If your interested what cache has to do with up-time in aerospace applications, here is a publicly available JPL paper. Here is a journal paper on it as well. – AustinTronics Oct 19 '16 at 17:40
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    Ironically, disabling the L1 cache makes sense, today! – e2-e4 Jan 7 '18 at 8:18
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You can accomplish this with a little ASM code, see chapter 11 of the Intel System Programming Guide

11.5.3 Preventing Caching

To disable the L1, L2, and L3 caches after they have been enabled and have received cache fills, perform the following steps: 1. Enter the no-fill cache mode. (Set the CD flag in control register CR0 to 1 and the NW flag to 0. 2. Flush all caches using the WBINVD instruction. 3. Disable the MTRRs and set the default memory type to uncached or set all MTRRs for the uncached memory type (see the discussion of the discussion of the TYPE field and the E flag in Section 11.11.2.1, “IA32_MTRR_DEF_TYPE MSR”).

I'm not aware of a Python module that implements this.

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