That's usually done with makefile rules, e.g., given
test.c, you would be able to do this (even without having a makefile):
Likewise, there are predefined rules for g++, given
test2.cc, you could do the same thing:
But in either case, you probably need libraries. Doing that is what makefiles are good for (in addition to providing ways of compiling multiple objects).
gcc by itself doesn't have an option to simulate makefile rules. If you want a tool which does that, you could make a shell script which does the special case mentioned, e.g.,
for name in "$@"
case "$name" in
gcc -o $(basename "$name") "$name"
g++ -o $(basename "$name") "$name"
echo "ignoring $name, since it is not one of my files!"
But (see the beginning of the answer), the script merely makes explicit the feature that the predefined rules for
make provide you. On the other hand, you could modify the script to add necessary libraries, and do that in one place (rather than a set of makefiles, which seems to be the issue).
By the way: whether gcc automatically provides a ".exe" suffix (when you do not) depends upon the platform and the compiler configuration. The suffix is not useful on Unix-like platforms and is generally optional on related things such as Cygwin.