I'm studying the book 'Operating System Concepts' 9th edition. In the first chapter, part 1.2.1 computer system operation, I can't understand the figure 1.3: The interrupt timeline for a single process doing output

Can any one make a quick interpretation on this for me? especially about the peaks of this graph?

  • Does it describes what X & Y axes do represent? – Pandya Mar 8 '16 at 13:45
  • @Pandya No, in the original text there isn't any label for them. – Peter Mar 8 '16 at 17:19
  • I do not have any doubts X are events in time. The Y seems pretty explanatory. – Rui F Ribeiro Mar 8 '16 at 19:45
  • That's right Pandya. It is showing a set of states for both the CPU and the I/O device in which interrupts are triggered and processed by I/O device and CPU, respectively. – Peter Mar 8 '16 at 20:00

The I/O device (controller) is busy transferring data from the device buffer to the device. It goes from idle to transferring. This is the peak for I/O device. It goes back to idle when the transfer is done, until the next request.

The CPU curve shows a peak when the transfer is done because the CPU is notified by the device (through an interrupt).

  • Thanks for the answer; so in fact, when the I/O device triggers an interrupt, the CPU stops user process executing for a while until the interrupt processing is done? – Peter Mar 8 '16 at 19:56
  • it depends on which cpu handles the interrupt. If there s a process running on that cpu, the interrupt is handled at the earliest opportunity as it has a higher priority - this will interrupt the running process. – jai_s Mar 9 '16 at 5:42

The graph obvious show the relation of the CPU states vs [device] output states over time.

The peaks in CPU time are when the CPU is busy doing it´s task or sleeping, depending whether it is doing synchronous or asynchronous writes.

The valleys in the CPU time are when the CPU is notified by an interrupt the device was finished, to proceed with setting up the buffers for the next round.

The peaks in the device are when it is idle waiting for output waiting for I/O requests, and the valleys when the device controller is writing the memory buffers independently of the CPU to the actual device. Often that writing is done via DMA. (Direct Memory Access)

  • Thanks for your comprehensive guidance through this graph. Now I have a better understanding about both the peaks and valleys for the CPU and the I/O device. – Peter Mar 8 '16 at 20:19

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