I am try to build a simple, two-stage project Makefile with GNU make.
The logic I want to follow is
- First I construct the dependencies (by
- I include the generated .dep files into the Makefile in a second stage build.
The relevant part of my project is the following:
MAKEDEP:=$(CXX) $(CXXFLAGS) -M ALL_SRCS:=$(ALL_OBJS:.o:.cc) CXX_DEPS:=$(patsubst %.o,.%.dep,$(ALL_OBJS)) -include $(CXX_DEPS) %.o: %.cc .%.dep $(CXX) $(CXXFLAGS) -c -o $@ $< .%.dep: %.cc $(MAKEDEP) -o $@ $< clean: $(RM) -vf $(ALL_OBJS) $(ALL_LIBS) $(ALL_APPS) dep: $(CXX_DEPS)
Everything works fine, with a single exception: if I run a
make clean, it rebuilds the dependencies! As if a
clean: dep line would exist instead of a simple
$ make clean g++ -Wall -std=c++11 -M -o .file1.dep file1.cc g++ -Wall -std=c++11 -M -o .file2.dep file2.cc g++ -Wall -std=c++11 -M -o .file3.dep file3.cc rm -vf file1.o file2.o file3.o app $
What is in the background? Why does it need to rebuild the dependencies before a cleanup? I didn't give such a dependency.