I'm using a Makefile to compile my Clean code. My Clean files have file names of the format
*.icl and are compiled to binaries with the same name but without
.icl. This is done with the rule:
$(EXE): % : %.icl | copy $(CLM) $(CLM_LIBS) $(CLM_INC) $(CLM_OPTS) $@ -o $@
I would now like to add a rule which allows me to run a binary. Currently, I'm often doing
make some_module && ./some_module
I would like to have a make target which depends on the rule above and runs the module. However, the name of the module is already a target itself for compilation alone and I'd like to keep it that way. What I would like is a target with two words that I can call with
make run some_module which then depends on the rule above and runs
Is it possible to create targets with multiple words?
I tried to make a rule (now still without dependency) with the following:
run $(EXE): ./$@
make run some_module results in many recipes being 'overridden' and 'ignored' and finally
./run not existing.
Makefile:24: warning: overriding recipe for target 'tut7_2_2' Makefile:21: warning: ignoring old recipe for target 'tut7_2_2' Makefile:24: warning: overriding recipe for target 'support_check' Makefile:21: warning: ignoring old recipe for target 'support_check' [...] Makefile:24: warning: overriding recipe for target 'drawingframe' Makefile:21: warning: ignoring old recipe for target 'drawingframe' ./run /bin/bash: ./run: No such file or directory Makefile:24: recipe for target 'run' failed make: *** [run] Error 127