Here is a breakdown of what is going on in this makefile:
There is a list of objects someplace, add "hello-1.o" to the list.
obj-m += hello-1.o
Create a target called all that has no requirements. The recipe to make all is to change in to the build directory in the directory that is named based on the current kernel release this system is running (which is in the modules directory under /lib). While we're at it save a variable that will contain the present working directory that we call this make from. Now find a make file in that directory we just changed into and build the target modules
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) modules
This one is almost the same and is left as an exercise for the reader:
make -C /lib/modules/$(shell uname -r)/build M=$(PWD) clean
The reason the clean isn't just a
rm is because the kernel has a lot of independent parts that all work together. Writing one monolithic makefile would be painful at best but really unmaintainable. Therefore each logical part of the build directory has it's own makefile that can be called from the coordinating makefile. Makefiles can get pretty hairy so it's bestto keep them focused and maintainable.