I have a Verilog line like this:
if (i2_0&!(i2_1)) (posedge i0_0 => (o:1'b1))=(0, 0);
How can I convert it to a line like:
if (i2_0 == 1'b1 & i2_1 == 1'b0) (posedge i0_0 => (o:1'b1))=(0, 0);
Basically I want to search the alphanumeric strings after the first bracket of the if statement and convert each section in between the brackets or the "&"s to their equivalent logic statement.
(i2_0 == 1'b1 &
i2_1 == 1'b0)
in the above example.