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Context: I'm reading "Understanding the Linux kernel, 3d ed", which uses the 2.6.11 kernel.

Question: As I understand, the physical address is obtained by translating the linear address, which is obtained by translating the logical address. The logical address consists of a segment selector, which identifies a segment in a Description Table

The Linux Global Description Table includes, amongst other segments, a user code and data segment. But the base address of both segments is 0x0, and their size is also the same. So they completely overlap. So as I understand, the logical address cs + offset is identical to the logical address ds + offset, where cs and ds are the CPU registers that hold respectively the code segment selector and data segment selector. I think this is the case because both segments have the same base address, which is incremented with the offset to get the linear address.

If this is the case, and they both map to the same linear address, don't they also map to the same physical address? If so, what is the use of having separate cs and ds registers?

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The segmentation registers are a legacy from the early days of the x86 processors, when the offset wasn't large enough to address all of the memory the processor could address. The original 8086 had a 20-bit address space, but could only use a 16-bit offset. You had to use the segment registers to specify which 64KB of the 1024KB address space you wanted. The segment registers were effectively 20-bit registers where the lowest 4 bits were forced to 0. Loading a segment register set the upper 16 bits of the register. This allowed segment + offset to cover the entire 20-bit address space.

The segment registers still exist, but Linux sets them to 0 so it can pretend they don't. Modern x86 processors (meaning the 80386 and newer) can use an offset big enough to cover all their address space, making memory segmentation a complication that's no longer necessary. Read x86 memory segmentation and the flat memory model for more details.

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  • so linux only uses paging and no segmentation in its memory management? – codd Jan 16 '14 at 18:24
  • Yes, that's correct. – cjm Jan 16 '14 at 18:25
  • Actually we have sort of a return to segment-like model with PAE, where 64G (36 bit) address space can only be addressed in 4G chunks by the application. – Ruslan Aug 29 '15 at 18:49
  • @cjm May I extend this question. When 20bit physical address was obtained by adding (16bit segment << 4) and 16bit offset, doesn't that mean , that one physical address can be obtained from multiple different pairs of segment and offset i.e. segments overlap? For example... 1010 + 0011 = 101011 and 1000 + 1011 = 101011 – Lukáš Řádek Jan 14 '18 at 12:23
  • @LukášŘádek, yes, that's true, and I'm sure there was software that did that for various reasons. The segmentation registers weren't really about memory protection, but just about expanding the address space. – cjm Jan 16 '18 at 20:24

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