101 reputation
1
bio website ieee-jbdavid.blogspot.com
location San Jose, CA
age 55
visits member for 3 years, 3 months
seen Aug 2 '11 at 0:33
Mixed Signal Design Verification languages: -Verilog (in all its flavors esp Verilog-AMS) -perl -SKILL (the cadence variant of LISP) -(someday) Python & Matlab

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