make is a utility that automates the build process by managing dependencies amongst targets.
The make utility is driven by optional configuration files (makefiles) and built-in rules that take components and create an output file, typically an executable file. The configuration files and built-in rules define how to create an output file from the given input files. The rules consist of a target, dependencies, and commands to execute to create the output file. If all of the dependency files are "up to date" in regards to the output file, no action is taken.
For example, if creating an executable file
hello.exe requires two source files,
hello.h then a makefile could look like this:
hello.exe: hello.c hello.h cc hello.c -i hello.h -o hello
If the timestamps for
hello.h are older than for
hello.exe then the
cc command is executed. There are numerous macros predefined that for simple tasks a simple makefile (or even no makefile) is needed.