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How can using huge page improve performance?

I have read that huge pages improve performance by reducing TLB lookups and reducing the size of the page table. Can someone tell me how this helps with performance?

Is this like if I have an application that uses 4 pages of virtual memory (4*4kb=16kb) then each page is mapped directly to some physical memory location, but if we use huge pages of 16kb size then instead of mapping 4 pages it just needs to map one, thus reducing page table size, and chances of swapping this out to disk is less and hence longer TLB cache?

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"thus reducing page table size and chances of swapping" -> non sequitur at the "and". It's not consequently of anything, it's by fiat: huge pages cannot be swapped. Note that using huge pages does not mean all memory is managed that way. You have X huge pages, the rest is normal. Great example of this here: pythian.com/blog/performance-tuning-hugepages-in-linux – goldilocks Feb 26 '13 at 9:46
Why performance is better with Huge page,also some article is mentioning about a patch that swaps Huge page,however since huge is large,swapping this can take more time than normal.I just need to know why there is performance benefit. – kevin Feb 26 '13 at 10:19
@kevin because the probability that your subsequent memory access causes TLB hit is much higher with 2Mb pages than with 4Kb pages. Thus, the overhead to get proper Page Table Entry is lower. – Serge Feb 26 '13 at 10:25
There isn't necessarily a performance benefit, there is a potential performance benefit depending on context. Depending on context and configuration, you could also just end up substantially reducing your amount of usable memory. So if you don't understand it or do not have a clear and definable need for it, just leave it alone. – goldilocks Feb 26 '13 at 10:31
up vote 3 down vote accepted

Serge answered it. The TLB has a fixed number of slots. If a virtual address can be mapped to a physical address with information in the TLB, you avoid an expensive page table walk. But the TLB cannot cache mappings for all pages.

Therefore, if you use larger pages, that fixed number of virtual to physical mappings covers a greater overall address range, increasing the hit ratio of the TLB (which is a cached mapping).

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