Makefile compiles unchanged files

Question

Made an effort to get the object files in another directory, but that directory would otherwise reflect the source directory tree. Got that to work, but there is a missing piece at the $(OBJ): line (right?), so wether you change the source or not, it recompiles. Have a look.

SRC_PATH=../src/
CC=g++
CFLAGS=-c -Wall
LDFLAGS=-lSDL -lSDL_gfx
INCL=-I $(SRC_PATH)include/
EXE=run

SRC=$(wildcard $(SRC_PATH)*.cpp $(SRC_PATH)game/*.cpp $(SRC_PATH)player/*.cpp)
OBJ=$(subst ../src, ../obj, $(SRC:.cpp=))
OBJ_O=$(addsuffix .o, $(OBJ))

all: $(SRC) $(EXE)

$(EXE): $(OBJ)
    $(CC) $(LDFLAGS) $(OBJ_O) -o $@

$(OBJ):
    $(CC) $(CFLAGS) $(INCL) -o $(addsuffix .o, $@) $(subst ../obj, ../src, $@).cpp

clean:
    rm -rf run $(OBJ_O)

Edit

This works as intended: does not recompile. Also, is much easier to read without the complicated suffixes back and forth. See answers and comments below.

SRC_PATH=../src/
CC=g++
CFLAGS=-c -Wall
LDFLAGS=-lSDL -lSDL_gfx
INCL=-I $(SRC_PATH)include/
EXE=run

SRC=$(wildcard $(SRC_PATH)*.cpp $(SRC_PATH)game/*.cpp $(SRC_PATH)player/*.cpp)
OBJ=$(subst ../src, ../obj, $(SRC:.cpp=.o))

all: $(SRC) $(EXE)

$(EXE): $(OBJ)
    $(CC) $(LDFLAGS) $(OBJ) -o $@

../obj/%.o: ../src/%.cpp
    $(CC) $(CFLAGS) $(INCL) -o $@ $<

clean:
    rm -rf run $(OBJ)

Answer 1

There are several problems:

First, your OBJ variable does not refer to a list of files that are built. E.g., when you have source files src/a.cpp and src/b.cpp, OBJ will contain obj/a and obj/b. So use OBJ_O instead of OBJ.

Second, your target for building the OBJ files does not give dependencies between the .cpp and .o files. It is a problem that you write your rule for creating the .o files in that way, because you can't give dependency info in that line. I would completely rewrite that rule for creating .o files:

../obj/%.o: ../src/%.cpp
    $(CC) $(CFLAGS) $(INCL) -o "$@" "$<"

This builds each .o file separately, and each .o file depends on the corresponding .cpp file.

This is a rule for creating a ../obj/**.o file from every file that matches ../src/**.cpp.

Answer 2

To make it clearer:

The main problem is precicely the line $(OBJ):

The problem is that if there is a source file ../src/a.cpp the variable OBJ contains ../obj/a and the rule $(OBJ): means "use the following recipie to build the file ../obj/a". But that's not what the recipie does! (Instead it creates a file ../obj/a.o.)

That's why make will always execute that recipie because it is desperate to create the file ../obj/a as that filename is listed as a depencency in $(EXE): $(OBJ)